一种支持细粒度并行的SDN虚拟化编程框架

软件定义网络(software defined network,简称SDN)通过集中式的控制器提高了网络的可编程性,成为近年来网络领域非常热门的话题。以Openflow网络为代表的软件定义网络将逻辑控制与数据转发相隔离,为网络虚拟化技术提供了良好的平台。集中式的抽象与控制使得SDN虚拟化框架的处理效率成为主要瓶颈。现有的SDN虚拟化框架由于缺乏对细粒度并行的支持,为编程人员充分利用多核/众核资源、控制更大规模的网络带来了极大的挑战。为了提高SDN虚拟化框架的处理效率,提出一种新的SDN虚拟化编程框架,通过新颖的API和运行时,在框架内部支持细粒度的并行处理。该框架通过对网络中流和网络资源进行抽象,使开发人员可以直接通过划分流空间来定义不同的虚拟网络,利用无锁的编程方式对共享的网络资源和流进行操作。实验结果表明,该框架在逻辑控制的执行效率方面具有良好的可扩展性,可以创建出更大规模的虚拟网络,并对其进行更为复杂的控制。     

ARM7处理器NUC710ADN扩充双网口设计

在ARM7处理器NUC710ADN的第一个网口的基础上,利用网口驱动芯片DM9000AEP扩充了第二个网口,使系统实现双网口通信。给出了硬件设计电路,对DM9000AEP的驱动程序在μClinux下的移植过程进行了描述,测试结果表明双网口都能正常可靠的工作,达到了ARM7处理器进行双网通信的功能要求。     

OpenMDSP: Extending OpenMP to Program Multi-Core DSPs

Abstract Multi-core digital signal processors （DSPs） are widely used in wireless telecommunication, core network transcoding, industrial control, and audio/video processing technologies, among others. In comparison with general-purpose multi-processors, multi-core DSPs normally have a more complex memory hierarchy, such as on-chip core-local memory and non-cache-coherent shared memory. As a result, efficient multi-core DSP applications are very difficult to write. The current approach used to program multi-core DSPs is based on proprietary vendor software development kits （SDKs）, which only provide low-level, non-portable primitives. While it is acceptable to write coarse-grained task-level parallel code with these SDKs, writing fine-grained data parallel code with SDKs is a very tedious and error-prone approach. We believe that it is desirable to possess a high-level and portable parallel programming model for multi-core DSPs. In this paper, we propose OpenMDSP, an extension of OpenMP designed for multi-core DSPs. The goal of OpenMDSP is to fill the gap between the OpenMP memory model and the memory hierarchy of multi-core DSPs. We propose three classes of directives in OpenMDSP, including 1） data placement directives that allow programmers to control the placement of global variables conveniently, 2） distributed array directives that divide a whole array into sections and promote the sections into core-local memory to improve performance, and 3） stream access directives that promote big arrays into core-local memory section by section during parallel loop processing while hiding the latency of data movement by the direct memory access （DMA） of a DSP. We implement the compiler and runtime system for OpenMDSP on PreeScale MSC8156. The benchmarking results show that seven of nine benchmarks achieve a speedup of more than a factor of 5 when using six threads.     

Memory E?cient Two-Pass 3D FFT Algorithm for Intelr Xeon PhiTM Coprocessor

Equipped with 512-bit wide SIMD instructions and large numbers of computing cores, the emerging x86-based Intelr Many Integrated Core (MIC) Architecture provides not only high floating-point performanc...     

Implementation-aware selection of the custom instruction set for extensible processors

This paper presents an approach for incorporating the effect of various logic synthesis options and logic level implementations into the custom instruction (CI) selection for extensible processors. This effect translates into the availability of a piecewise continuous spectrum of delay versus area choices for each CI, which in turn influences the selection of the CI set that maximizes the speedup per area cost (SPA) metric. The effectiveness of the proposed approach is evaluated by applying it to several benchmarks and comparing the results with those of a conventional technique. We also apply the methodology to the existing serialization algorithms aimed at relaxing register file constraints in multi-cycle custom instruction design. The comparison shows considerable improvements in the speedup per area compared to the custom instruction selection algorithms under the same area-budget constraint.     

数字化逆变式等离子切割电源的研制

提出了一种基于数字信号处理器(DSP)和单片机(MCU)并行处理技术,实现数字化逆变式等离子切割电源的新方法,利用DSP高速强大的数据处理能力,实现切割参数的采样计算和相应控制算法;采用控制能力强大的单片机实现人机接口和逻辑控制.设计专用的保护电路、参数记忆电路和自动调高模块,实现对过压/过流保护、最佳系统参数匹配和割炬调整.实验数据表明,智能数字化切割电源控制性能好,可靠性高和操作灵活,大大改善了切割质量.     

实时桥梁缆索健康监测系统硬件设计

针对一种以16/32位ARM处理器为核心的用于桥梁缆索张力的实时监测系统的主控制器部分硬件设计过程进行了介绍.通过高功能、低功耗的LPC2138,12位4通道的A/D转换MAX1247和GPRS模块M23G,实现了桥梁缆索监测系统数据采集与发送的硬件设计和检测.经测试,本系统在实验室阶段最高采样速率为62.5 KB,实际GPRS网络传输速率为40 KB左右,完全满足缆索张力监测要求.最高频率为10 KB.     

基于DSP的VSR变换器SVPWM信号的产生

实现了基于数字信号处理器（Digital Signal Processor-DSP）的空间矢量脉宽调制（Space Vector Pulse Width Modulation——SVPWM）系统,并将其应用于电压型整流器（Voltage Source RectifierVSR）触发系统中。相比较于其它脉冲宽度调制技术,采用的SVPWM具有算法简单、适用于数字实现、电压利用率高、开关损耗小以及硬件电路简单等特点。实验结果表明,设计的基于DSP的SVPWM脉宽调制系统达到VSR触发系统的要求,为VSR装置正常、有效地工作提供了重要保证。     

密码指令集扩展研究*

详细分析了常见密码算法的基本操作以及密码指令集扩展的研究现状,针对当前密码系统需要支持多种密码算法的特点指出未来密码指令集扩展的发展方向:指令设计需朝通用性上发展且通用密码处理器是处理器密码指令集扩展的最终目的。     

面向网络处理器的软件组件技术研究*

基于网络处理器的系统是一种复杂的嵌入式系统,具有实时、资源受限和异构的特点.组件技术可以实现有效的软件开发,但是通用的组件技术不适合基于网络处理器的系统.研究将组件技术应用于基于网络处理器的系统的问题,分析了硬件系统结构和目标应用的特点,提出了组件模式,定义了框架服务,并讨论了软件性能工程.其组件技术也适用于其他类似的多核系统.